SOURCE-LINKED INTELLIGENCE

Para-Pipe: Exploiting Hierarchical Operator Parallelism of ML Computational Graphs on SoCs

arXiv · AI, language, vision and robotics · article · Sep 3, 2026 · UTC

As edge-based deep learning applications become more complex, optimizing performance on heterogeneous System-on-Chips (SoCs) presents unique challenges. Traditional pipelining techniques distributing the computation across different on-chip processing units, while effective for throughput, do not address the latency demands posed by modern neural networks with complex interdependencies and extensive operator parallelism. There is a potential in leveraging operator parallelism to enable concurrent execution across multiple processing units, thereby reducing inference latency. However, prioritiz

Read original source ↗ Open in workspace

recordType

paper

region

Global