SOURCE-LINKED INTELLIGENCE

An LLM-Resilient Tool for Safe RTL Sharing

CORDIS · observation · Publication date unknown

r development, it also exposes valuable design assets to reverse engineering and unauthorized reuse. These risks are rapidly increasing with the emergence of AI models for code understanding, such as large language models, which can infer the functionality and intent of hardware designs. Existing protection mechanisms provide only limited protection against AI-assisted design analysis. The ERC Proof-of-Concept project, MIRAGE, led by Ahmad-Reza Sadeghi, addresses this very challenge. It automatically transforms RTL code — the hardware description language used for chip circuitry — in a way that preserves its functionality while rendering it virtually unrecognizable to AI systems. This allows companies to share their designs more securely, without exposing commercially sensitive information. MIRAGE builds on HYDRANOS, a project awarded an ERC Advanced Grant in 2022, which protects chips against unknown attacks by enabling security-critical components to be adapted after manufacturing. MIRAGE now extends this protection upstream, to the level of the design itself.

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recordType

award

status

SIGNED

region

EU

value

150000

unit

EUR